In general, a FET is a three-terminal device which may find use in both microwave amplification and switching. The three terminals on the FET include a gate, source and drain. A basic FET includes a gallium arsenide (GaAs) substrate with an active layer arranged thereon. The active layer includes a source and a drain, with a gate arranged therebetween on top of the active layer. The FET may also include a backside metal on the bottom of the substrate. The backside metal may be configured to be in electrical communication with the source by a plated via hole through the substrate.
In operation, a voltage signal applied to the gate creates a depletion or inversion region in the active region between the source and the drain. This region allows current to flow between the source and the drain, respectively. In typical microwave and RF applications, the drain is the output of the device. FETs can be structured in the form of a FET prime cell which has better frequency and power properties then the basic FET design. The prime cell provides the gate, source, drain, substrate and wiring configuration to make an RF amplifier.
Although offering improved frequency and power characteristics, typical FET prime cell configurations include a relatively large footprint of the device due to the various features of the FET prime cell spread across the top region of the substrate. Additionally, typical FET designs include the wiring related capacitance between the gate fingers to the substrate. There is also wiring related capacitance between the source fingers and the substrate. Neither of these wiring related capacitances scale with shrinking device geometry, and thus become difficult to improve at ever smaller device sizes. These wiring related capacitances lead to a reduction in the maximum workable frequency of the device and thus imposes frequency limitation on the FET prime cell.
For example, FIGS. 1 and 2 show a typical FET prime cell 100. The FET prime cell 100 includes a substrate 122 with alternating or interleaved source contacts and drain contacts, 104 and 106, respectively, arranged thereon. Also arranged on the substrate 122 are gate fingers 102 between the source contacts and drain contacts 104 and 106. The gate fingers 102 are interconnected with one another by a metal ring 108. The metal ring 108 forms a conductive ring around the region of the substrate 122 on which the gate fingers, source contacts, and drain contacts, 102, 104 and 106, are arranged.
Arranged in the substrate 122 surrounding the active region of the FET 100 is a shallow trench isolation 120 which is surrounded by a ring substrate contact 118 (e.g., the ring substrate contact 118 is arranged adjacent and outboard of the shallow trench isolation 120). The ring substrate contact 118 provides electrical contact to substrate 122. The outer-most sources 114 have the shallow trench isolation 120 arranged on either outboard side.
Accordingly, typical FET designs also include an explicit substrate contact which leads to requiring a unique wiring of the gate. The required wiring is not optimal for device operation and adds an undesirable design constraint for circuit designers. Also, typical related art designs cause wiring parasitics which may prevent the substrate from actually being at the same potential as the source. Additionally, the combination of the shallow trench isolation adjacent the ring substrate contact may make the typical FET more susceptible to stray currents and other electrical noise.